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MC33567
Advance Information Dual Linear Controller for High Current Voltage Regulation
The MC33567 Dual Linear Controller is designed for motherboard/mainboard applications requiring reliable regulation of high current supply planes. This advanced linear IC provides the necessary drive, sense, and control signals to interface two separate N-channel MOSFETs as individual series pass elements regulating two different supply planes. Use of this device lowers costs as well as ameliorates layout problems on pc motherboard products. Additionally, an under voltage-based short circuit detection and protection feature is provided which places system operation into a protected mode pending removal of the short.
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SO-8 D SUFFIX CASE 751
* Detects under voltage condition (short circuit condition) and places * *
regulation into a protective "hiccup" mode, thus preventing damage and permitting recovery after short circuit condition is corrected Drive capability for SOT-223, DPAK, and D2PAK MOSFETs MC33567-1 controls two separate series pass transistors to provide regulation for separate 1.5V and a 1.8V supply planes. MC33567-2 controls two separate series pass transistors to provide regulation for separate 2.5V supply planes
Simplified Functional Block Diagram
+3.3Vin 8 +12V 4 GND BandGap REF 3.3V 66k 3 SHDN1 Vin Bypass On BandGap REF 3.3V 66k 5 SHDN2 REF 4.1V
This document contains information on a new product. Specifications and information herein are subject to change without notice.
PIN CONNECTIONS
1 8 7
Gate1 drv
2
Sense1
3
Vcc Gate2 drv Sense2 Shutoff2
Shutoff1 GND
4
MC33567
6 5
1 DRV1
+12V Control 2 SNS1 Vout1
ORDERING INFORMATION
Device MC33567D-1 +3.3Vin 7 DRV2 MC33567D-1R2 MC33567D-2 MC33567D-2R2 Control 6 SNS2 Vout2 Output Voltage 1.8V, 1.5/3.3V Shipping 98 Units/Rail
Startup and Overcurrent Control
1.8V, 1.5/3.3V 2500 Tape&Reel 2.5V, 2.5V 2.5V, 2.5V 98 Units/Rail 2500 Tape&Reel
+12V
Startup and Overcurrent Control
(c) Semiconductor Components Industries, LLC, 1999
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January, 2000 - Rev. 0
Publication Order Number: MC33567/D
MC33567
MAXIMUM RATINGS
Parameter Supply Voltage Operating Ambient Temperature Operating Junction Temperature Lead Temperature (Soldering, 10 seconds) Storage Temperature Range Package Thermal Resistance, Junction to Ambient Symbol Vcc Ta TJ TL Tstg RJA1 Max Value 12.5 0 to +80 - 5 to +125 300 - 55 to +150 180 Unit Vdc C C C C C/W
DEVICE MARKING
Device MC33567-1 MC33567-2 Type 1.818 V, 1.515 V 2.525 V, 2.525 V Package SO-8 SO-8 Marking (1st Line) M5671 M5672
PIN ASSIGNMENTS AND FUNCTIONS
PIN # 1 2 3 4 5 6 7 8 PIN NAME Gate 1 drive Sense 1 line Shutoff 1 Ground Shutoff 2 Sense 2 line Gate 2 drive 12 volt input At TTL high level turns off regulation for gate 2. Effectively grounds gate 2. (Internal pullup to 3.3V) Returns regulated output from mosfet. Drives mosfet in linear region. Is internally clamped to ground in power down mode. Supply voltage for operation and gate drive output. PIN DESCRIPTION Drives mosfet in linear region. Is internally clamped to ground in power down mode. Returns regulated output from mosfet. At TTL high level turns off regulation for gate 1. Effectively grounds gate 1. (Internal pullup to 3.3V)
ELECTRICAL CHARACTERISTICS
Characteristic Output Voltage Regulation (Full-load to no-load @ 25 - 70C) Peak Gate Drive Output (pin 1, pin 7) Drive Sink Current (steady state) Short Circuit / Undervoltage Detect (load current increased until output drops) Quiescent Current Under Voltage Lock Out Hysteresis Shutoff Threshold (Lower) Shutoff Hysteresis Short Circuit Response Time Short Circuit Off Time Short Circuit On Time Shutoff Disable Time Symbol Vreg% Ipkdrv Isink ss/uvd Iq UVLO hys SHDN SHDNhys SCtd SCtoff SCton SHDNtdis Min -2.5 10 5.0 70 -- 7.0 0.2 0.8 -- -- 20 0.5 -- Typ -- 20 7.0 -- 7 8.5 0.5 1.13 130 250 40 0.8 0.5 Max +2.5 30 10 80 10 9.0 0.9 1.29 -- -- 60 1.5 2.0 Unit % mA mA % Vo mA V V V mV
mS
mS mS S
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MC33567
Figure 1. MC33567 Detailed Functional Block Diagram
VCC VCC 8 DRV1 1 SNS1 2 REG 1.818V DRV Vref SNS On Off 5V Vfb In1 In2 In3 In1 In2 In3 5Vreg Vref REG 1.515V Vref DRV Off On SNS Vfb DRV2 7 SNS2 6
REF
Vref Vref_75%
Vref UVLO UVLO
OR
*
SHDN1 3 SHDN Bypass On COMP Hys Vref 5V Out
FAULT_LOGIC UVLO 5V Fault_Out Vref SHDN_In Fault
FAULT_LOGIC 5V UVLO Vref Fault_Out Fault SHDN_In
OR
SHDN2 Bypass On SHDN COMP Hys Out 5V Vref 5
Neg Pos COMP GND 4 VSS 5V
Out
GLITCH FILTER In Out Vref 5V
GLITCH FILTER Out In Vref 5V
Out 5V
Neg COMP Pos
* Internal ground disables Bypass On Function on the 1.8V regulator in
the MC33567-1 and on the 2.5V regulators of the MC33567-2.
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MC33567
FUNCTIONAL DESCRIPTION Overcurrent Protection - Hiccup Mode On detection of overcurrent, output goes into hiccup mode where on period is 40 times shorter than off time. I.e., 1.0 msec ON, 40 msec OFF. When an overcurrent condition exists, the output voltage will drop below the threshold. The Shutoff (Shutdown) Function Each internal regulator has an active high enable input. If the input is held above the minimum threshold, the regulator
Logic table for Shutoff (Pin 3) on the 1.5V regulator:* Shutoff Pin No Connect < 0.8V 2.0V < SHDN < 4.2V > 4.1V 1.5V Regulator Output 1.5V Shutoff 1.5V 3.3V - Full ON
output is then turned on and off in a 1:40 duty cycle. Each transition low to high of the enable input restarts the hiccup mode holdoff period.
will operate normally. If the input is held low, the regulator is turned off.
Logic table for Shutoff (Pin 3) on the 1.8V regulator: Shutoff Pin No Connect < 0.8V > 2.0V 1.8V Regulator Output 1.8V Shutoff 1.8V
*See Figure 4, 1.5V / 3.3V AGP card detection NOTE: MC33567-2 does not have full-on bypass feature
This part has under voltage detection that uses the channel resistance of an internal N-channel FET to put the regulator into "hiccup mode" when a short is present on the regulated
voltage plane. Under voltage detection is set to regulation set point.
75% of
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MC33567
200 PHASE PHASE MARGIN = 48 @ 8 kHz PHASE MARGIN = 60 @ 200 kHz GAIN dB 0 ILOAD = 2 A C = 200 mF Resr = 50 mW -100 101 102 103 104 f, FREQUENCY 105 106 -100 0 ILOAD = 2 A C = 200 mF Resr = 200 mW 101 102 103 104 f, FREQUENCY 105 106 200 PHASE *PHASE MARGIN = 85 @ 8 kHz PHASE MARGIN = 48 @ 500 kHz GAIN dB
100
100
Figure 2. Gain-Phase Plot @ 50 mW
Figure 3. Gain-Phase Plot @ 200 mW
*NOTE: For adequate phase margin, C X R 10 X 10-6. E.g. 200 mF X 50 mW = 10 X 10-6, 400 mF X 25 mW = 10 X 10-6, 800 mF X 12.5 mW = 10 X 10-6.
Capacitor Selection Guidelines The goal here is to preserve adequate phase margin for stable operation. For adequate phase margin, the load capacitance ESR value multiplied by the load capacitance must be greater than 10x10-6. For example, if the load capacitor is 400F, then the ESR value of the capacitor would need to be no less than 25 milliOhms, (400F x 25mOhm = 10x10-6). Similarly, if the load capacitance was 200F, then the ESR value of the capacitance would need to be at least 50 milliOhms, (200F x 50mOhm = 10x10-6). (Important Note: The foregoing rule assumes that all capacitors across the load are of the same type and value. If different types and values of capacitors are used in parallel across the load, then each individual capacitors must meet the C x ESR > 10x10-6 rule).
PIN 5 TRUTH TABLE Pin 5 No connect = 1.5V LDO drive out active Pin 5 < 0.8V = shutoff (drive out 0V) 2.5V < pin 5 < 4.1V = 1.5V LDO drive out active Pin 5 > 4.1V = 3.3V bypass mode (drive out = Vcc)
PCB Layout Guidelines The goal here is to minimize extraneous signals from being either magnetically or electrostatically induced on the sense lines or drive lines. As much as practical, the LDO control ic should be physically close (short traces) to the external series pass transistors; the layout of the sense trace should parallel, go in the same direction, and be on the same plane as the power trace going from the series pass transistor source lead to the load; routing the sense lead near the load current return path should be avoided; unterminated runs of the sense lead should be avoided (if options on sense lead destinations are desired on the board, then use zero ohm resistor jumpers to make the alternate sense lead connections near the sense pin itself).
3.3Vin
AGP Card Voltage 1.5V/3.3V
AGP Card Type Detection
3.3Vin
12Vin
R7 10k
1 2 3 4 8 1.8V 1.5V 7 MC33567 6 5
Gate 2 drv Sense2 Shutoff2
Figure 4. 1.5V/3.3V AGP card detection
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MC33567
PACKAGE DIMENSIONS
SO-8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751-06 ISSUE T
A
8
D
5
C
E
1 4
H
0.25
M
B
M
h B C e A
SEATING PLANE
X 45 _
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETER. 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A A1 B C D E e H h L MILLIMETERS MIN MAX 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 4.80 5.00 3.80 4.00 1.27 BSC 5.80 6.20 0.25 0.50 0.40 1.25 0_ 7_
q
L 0.10 A1 B 0.25
M
CB
S
A
S
q
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MC33567
Notes
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MC33567
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
North America Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada EUROPE: LDC for ON Semiconductor - European Support German Phone: (+1) 303-308-7140 (M-F 2:30pm to 5:00pm Munich Time) Email: ONlit-german@hibbertco.com French Phone: (+1) 303-308-7141 (M-F 2:30pm to 5:00pm Toulouse Time) Email: ONlit-french@hibbertco.com English Phone: (+1) 303-308-7142 (M-F 1:30pm to 5:00pm UK Time) Email: ONlit@hibbertco.com ASIA/PACIFIC: LDC for ON Semiconductor - Asia Support Phone: 303-675-2121 (Tue-Fri 9:00am to 1:00pm, Hong Kong Time) Toll Free from Hong Kong 800-4422-3781 Email: ONlit-asia@hibbertco.com JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-8549 Phone: 81-3-5740-2745 Email: r14525@onsemi.com Fax Response Line: 303-675-2167 800-344-3810 Toll Free USA/Canada ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative.
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MC33567/D

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